AQA A-Level Computer Science (7517)

## Learning Outcomes

- Explain how **clock speed**, **cache memory**, and **number of cores** affect processor performance
- Distinguish between **word length**, **data bus width**, and **address bus width**
- Apply performance ideas to realistic exam comparisons between processors
- Use performance formulas carefully, including the link between **clock rate**, **clock cycle time**, and **CPI**
- Explain why a higher specification does not always mean proportionally higher real-world performance
- Recognise common misconceptions about multi-core processors, cache, and clock speed

## AQA A-Level Computer Science (7517) Syllabus

For the AQA A-Level Computer Science (7517), you are expected to understand processor performance factors, with a focus on the following syllabus points:

![Processor performance factors including clock speed, cache memory, core count, word length, data bus width, and address bus width.](https://static.pastpaperhero.com/images/aqa-a-level-computer-science-7517-computer-organisation-and-architecture-processor-performance-factors_00.png)

_Clock rate, cache size, core count, word length, and bus widths are identified as determinants of CPU performance._

- Know that processor performance is affected by **clock speed**, **cache size**, and **number of cores**
- Identify how **word length** affects the amount of data the CPU can process as one unit
- Understand how **data bus width** affects how much data can be transferred at once
- Understand how **address bus width** affects the maximum addressable memory
- Explain why increasing one factor alone does not always produce a matching increase in overall performance
- Apply processor performance knowledge to exam scenarios comparing different systems
- Use accurate terminology when describing the fetch-decode-execute cycle and delays caused by memory access

## Test Your Knowledge

_Attempt these questions before reading this article. If you find some difficult or cannot remember the answers, look more closely at that area during your revision._

1. Why does a processor with a higher clock speed not always run programs faster than another processor?
2. How does cache memory improve performance during the fetch-decode-execute cycle?
3. Why might a quad-core processor fail to give four times the performance of a single-core processor?
4. What is the difference between **word length**, **data bus width**, and **address bus width**?
5. If a processor has a 32-bit address bus, how does that affect memory access compared with a 16-bit address bus?

## Introduction

Processor performance is about how quickly and efficiently a CPU can carry out instructions. In exam questions, students often give vague answers such as “it is faster because it has more GHz” or “more cores means better performance”. That is too simple for AQA. Good answers explain the mechanism: what the processor is waiting for, what can happen at the same time, and what hardware limit is being reduced.

This topic sits inside computer organisation and architecture because performance depends on how the processor works with memory, buses, and the fetch-decode-execute cycle. A CPU can only execute instructions quickly if it can fetch instructions and data quickly enough as well.

> **Key Term: processor performance**
> The speed and efficiency with which a processor executes instructions and processes data.

### Clock speed and clock cycles

The **clock** generates regular timing signals that synchronise processor activity. Each tick of the clock allows hardware operations to start or move to the next stage. Clock speed is measured in **hertz (Hz)**, usually **gigahertz (GHz)** for modern processors.

> **Key Term: clock speed**
> The number of clock cycles per second, measured in hertz.

A processor running at 3 GHz has 3 billion clock cycles each second. In general, more cycles per second means the CPU has more opportunities to carry out work. That is why higher clock speed usually improves performance.

However, this does not mean clock speed is the same as “instructions per second”. Some instructions complete in one cycle, but many take several cycles. A complex instruction may involve fetching data from memory, carrying out an ALU operation, then writing the result back. If the processor has to wait for RAM, those extra cycles reduce overall speed.

A more accurate way to think about performance is:

- **Clock speed** tells you how many cycles are available per second
- **CPI** tells you how many cycles each instruction needs on average
- Performance improves when the processor can complete useful work in fewer cycles, not just when the clock ticks faster
  > **Key Term: clock cycle**
  > One tick of the processor clock, used to synchronise operations inside the CPU.

You may also meet this relationship:

CPU time = instruction count × CPI × clock cycle time

Since clock cycle time = 1 / clock speed, this can also be written as:

CPU time = (instruction count × CPI) / clock rate

This matters because two processors with different clock speeds can still perform differently if one needs fewer cycles per instruction.

Worked example:

A processor runs at **2 GHz** and has an average **CPI of 4**.

1. Clock rate = 2,000,000,000 cycles per second
2. Instruction rate = clock rate / CPI
3. Instruction rate = 2,000,000,000 / 4
4. Instruction rate = 500,000,000 instructions per second

So the processor completes **500 million instructions per second** on average.

Now compare that with a 1.5 GHz processor with CPI of 2:

1. Clock rate = 1,500,000,000 cycles per second
2. Instruction rate = 1,500,000,000 / 2
3. Instruction rate = 750,000,000 instructions per second

Even though the second processor has the lower clock speed, it completes more instructions per second because each instruction needs fewer cycles.

Common student errors:

- Saying clock speed means “instructions per second”
- Assuming one clock cycle always equals one instruction
- Assuming the highest GHz value automatically means the fastest processor
  > **Test Tip:** If an exam asks you to explain clock speed, define it as **cycles per second**, then explain that performance also depends on how many cycles each instruction needs and whether the CPU must wait for memory.

There is also a practical limit. Increasing clock speed increases heat output and power consumption. If the processor gets too hot, errors become more likely and the system may need throttling or stronger cooling. So faster clock speed can improve performance, but it has costs.

### Cache memory and memory access delay

A major reason processors lose time is that **RAM is much slower than the CPU**. The CPU may be ready to continue, but if the next instruction or item of data has to be fetched from main memory, the processor waits.

> **Key Term: cache memory**
> A small amount of very fast memory in or near the CPU that stores frequently used data and instructions.

Cache improves performance by storing instructions and data that are likely to be needed again soon. During the fetch-decode-execute cycle, if the required item is already in cache, the CPU gets it much faster than if it had to access RAM.

This links directly to real processor behaviour:

- The CPU fetches an instruction
- It may soon need the next instruction in sequence
- It may also need the same data again in a loop
- If those items are in cache, the fetch stage is quicker
- Less time is wasted waiting, so more cycles are spent doing useful work
  > **Key Term: cache hit**
  > When the data or instruction needed by the CPU is found in cache memory.
  >
  > **Key Term: cache miss**
  > When the required data or instruction is not in cache and must be fetched from main memory.

A larger cache often improves performance because it increases the chance of a **cache hit**. But the benefit is not unlimited. Cache is expensive and very fast memory, so large amounts are costly. Also, once the cache is already large enough for a task’s working set, adding even more may make little difference.

There are usually different levels of cache:

- **L1 cache**: smallest and fastest, very close to the core
- **L2 cache**: larger, slightly slower
- **L3 cache**: larger again, often shared between cores

You do not usually need detailed sizes in the exam, but you should know that lower-level caches are faster and smaller.

Worked example:

Imagine a loop that repeatedly adds values from a small array.

Without useful cache:

- Instruction fetched from RAM
- Data fetched from RAM
- Next loop instruction fetched from RAM again
- CPU repeatedly waits on slower main memory

With useful cache:

- First access copies instructions and data into cache
- Repeated loop accesses use cache instead of RAM
- Fewer delays occur
- Overall completion time falls

The key idea is not “cache stores everything”. It stores the most recently or frequently used items, so nearby and repeated accesses become faster.

Common student errors:

- Confusing cache with RAM
- Saying cache is a type of long-term storage
- Saying cache makes the clock speed faster

Cache does not increase clock speed. It reduces the number of slow memory accesses, so the processor spends less time idle.

> **Test Tip:** In “explain” questions, link cache to the **fetch-decode-execute cycle**. State that frequently used instructions/data are kept near the CPU, so the processor accesses RAM less often and wastes fewer cycles waiting.

### Cores, parallel processing, and realistic limits

A **core** is an individual processing unit inside the CPU. A multi-core processor contains multiple cores on one chip, and each core can run its own fetch-decode-execute cycle.

> **Key Term: core**
> An individual processing unit within a processor, capable of fetching and executing instructions.
>
> **Key Term: multi-core processor**
> A processor containing two or more cores on a single chip.

This means a dual-core processor can work on two streams of instructions at the same time, and a quad-core processor can work on four. That usually improves performance in two situations:

- **Multitasking**: several programs or background tasks are running at once
- **Parallel processing**: one program is split into multiple threads that can run at the same time

For example, a user might be:

- streaming music
- running a virus scan
- editing a document
- browsing the web

On a single-core system, the processor must switch rapidly between tasks. On a multi-core system, more of those tasks can genuinely run simultaneously.

But more cores do not guarantee a proportional speed-up. A quad-core processor is not automatically four times faster than a single-core processor.

Why not?

1. **Some tasks are serial**
   - One instruction depends on the result of the previous one
   - The work cannot be split safely between cores

2. **Software may be single-threaded**
   - Some programs are written to use only one main execution thread
   - Extra cores then bring little benefit to that program

3. **There is overhead**
   - Splitting tasks into threads takes management time
   - Data may need sharing or synchronising between threads
   - This reduces the gain

4. **Other bottlenecks remain**
   - RAM access, cache size, and bus width can still limit performance
   - Idle cores do not help if all threads are waiting for data

Worked comparison:

Processor A:

- 1 core
- 4.0 GHz

Processor B:

- 4 cores
- 3.0 GHz

Which is better?

A poor answer says “B is better because it has more cores” or “A is better because 4.0 is bigger than 3.0”.

A strong answer says:

- For a single-threaded game engine or old application, **A** may perform better because higher single-core speed matters more
- For video rendering, simulation, or running many tasks at once, **B** may perform better because work can be split across multiple cores
- The real answer depends on whether the software can use parallel processing efficiently

This kind of conditional judgement is what stronger AQA answers do well.

### Word length, bus width, and related factors

AQA often centres performance on clock speed, cache size, and number of cores, but textbook treatment also includes **word length**, **data bus width**, and **address bus width**. These matter because they affect how much data can be handled or transferred in one operation.

> **Key Term: word length**
> The number of bits the CPU can process as a single unit.

A 64-bit processor can usually manipulate larger values in one operation than a 32-bit processor. This is useful in data-intensive applications, large integer arithmetic, and memory addressing. If a processor can handle more bits at once, some tasks require fewer operations.

Example:

- Adding two 16-bit values on a 16-bit processor can be done in one main operation
- Doing the same on an 8-bit processor may require splitting the values into parts and handling carry bits across multiple steps

So larger word length can improve speed because fewer cycles are needed for the same amount of data.

> **Key Term: bus width**
> The number of bits that can be transferred along a bus in one operation.

There are two especially relevant buses here.

Data bus width

- Determines how many bits of data can be transferred at once
- A wider data bus means more data can move between processor and memory in each transfer
- This can reduce the number of transfers needed

Example:

- A 32-bit value on a 16-bit data bus needs two transfers
- The same value on a 32-bit data bus needs one transfer

Address bus width

- Determines how many memory addresses can be generated
- If the address bus has width n, the maximum number of addresses is 2^n
- A wider address bus allows more memory to be addressed

Worked example:

If the address bus is **16 bits** wide:

Maximum addresses = 2^16 = 65,536

If the address bus is **32 bits** wide:

Maximum addresses = 2^32 = 4,294,967,296

This does not directly mean the processor executes each instruction faster. Instead, it means the system can address more memory, which supports larger programs and data sets more effectively.

Students often confuse these ideas:

- **Word length** = how much data the CPU handles internally as one unit
- **Data bus width** = how much data moves in one transfer
- **Address bus width** = how many memory locations can be addressed

These are related, but not identical.

One extension idea is **pipelining**.

> **Key Term: pipelining**
> A technique where different stages of multiple instructions are overlapped so several instructions are in progress at once.

If one instruction is being decoded while another is fetched and another is executed, the processor can improve **throughput**.

> **Key Term: throughput**
> The amount of work, such as completed instructions, done in a given time.
>
> **Key Term: latency**
> The time taken for one specific task or instruction to complete.

Pipelining mainly improves throughput, not the latency of one single instruction. A single instruction may still take a similar total time from start to finish, but more instructions are completed per second overall.

This distinction is useful in evaluation questions because students often say pipelining makes each instruction faster. More accurately, it allows instruction stages to overlap, increasing the rate of completion.

## Key Point Checklist

_This article has covered the following key knowledge points:_

- Processor performance depends on several interacting factors, not one number alone
- **Clock speed** is the number of clock cycles per second, measured in Hz or GHz
- A higher clock speed usually improves performance, but only if the processor can make effective use of those cycles
- One instruction may take multiple clock cycles, so clock speed is not the same as instructions per second
- **Cache memory** is small, fast memory near the CPU that stores frequently used data and instructions
- A larger or more effective cache reduces slow accesses to RAM and improves performance
- A **cache hit** means the needed item is found in cache; a **cache miss** means it must be fetched from RAM
- More **cores** allow more tasks or threads to run at the same time
- More cores do not always give proportional speed gains because some tasks are serial and some software is single-threaded
- **Word length** affects how many bits the CPU can process as one unit
- **Data bus width** affects how many bits can be transferred at once, while **address bus width** affects the maximum addressable memory
- **Pipelining** improves throughput by overlapping instruction stages, but does not necessarily reduce the latency of a single instruction

## Key Terms and Concepts

- processor performance
- clock speed
- clock cycle
- cache memory
- cache hit
- cache miss
- core
- multi-core processor
- word length
- bus width
- pipelining
- throughput
- latency


Computer Organisation and Architecture - Processor performance factors